3.3V Wide-Range General Purpose Staggered I/O Pad Set
These libraries are offered at both 16nm and a 12nm shrink. They
are available in inline and staggered CUP wire bond implementations with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 3.3V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection. spacer cells
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GPIO IP
- APB4 General Purpose Input/Output Module
- DO-254 AXI General Purpose Input/Output (GPIO) 1.00a
- A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 22nm Wirebond IO library with dynamically switchable 1.8V/3.3V GPIO, 3.3V I2C open-drain, & analog cells
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell