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3.3V Wide-Range General Purpose Staggered I/O Pad Set
The 3.3V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibility to design to a wide range of performance targets.
These libraries are offered at both 16nm and a 12nm shrink. They
are available in inline and staggered CUP wire bond implementations with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 3.3V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection. spacer cells
These libraries are offered at both 16nm and a 12nm shrink. They
are available in inline and staggered CUP wire bond implementations with a flip chip option.
To design a functional I/O power domain with these cells, an additional library is required – 3.3V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection. spacer cells
Features
- Bidirectional GPIO Driver Features
- ▪ Multi-Voltage (1.2V, 1.8V, 2.5V, 3.3V)
- ▪ LVCMOS / LVTTL input with selectable hysteresis
- ▪ Programmable drive strength (rated 2mA to 12mA)
- ▪ Selectable output slew rate
- ▪ Optimized for EMC with SSO factor of 8
- ▪ Open-drain output mode
- ▪ Programmable input options (pull-up/pull-down/repeater)
- ▪ Power-On Start (POS) capable
- ▪ Power sequencing independent design with Power-On Control
- In full-drive mode, this driver can operate to frequencies in excess of 100MHz with 15pF external load and 125 MHz with 10pF load. Actual frequency limits are load and system dependent. A maximum of 200 MHz can be achieved under small capacitive loads.
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
View 3.3V Wide-Range General Purpose Staggered I/O Pad Set full description to...
- see the entire 3.3V Wide-Range General Purpose Staggered I/O Pad Set datasheet
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GPIO
- APB4 General Purpose Input/Output Module
- A 28nm 1.8V-3.3V Fail-Safe General-Purpose IO & OSC
- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF