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3.3V Wide Ranging GPIO
The 3.3V General Purpose I/O libraries provide bidirectional I/O, isolated analog I/O, and a full complement of I/O power, core power, and
analog power cells along with the necessary support cells to construct a complete pad ring by abutment. An included rail splitter allows
multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
analog power cells along with the necessary support cells to construct a complete pad ring by abutment. An included rail splitter allows
multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.
Deliverables
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
View 3.3V Wide Ranging GPIO full description to...
- see the entire 3.3V Wide Ranging GPIO datasheet
- get in contact with 3.3V Wide Ranging GPIO Supplier
GPIO IP
- APB4 General Purpose Input/Output Module
- A 28nm Wirebond IO library with dynamically switchable 1.8V/ 3.3V GPIO, 5V I2C open-drain, 1.8V & 3.3V analog, OTP program cell, and HDMI & LVDS protection macros - featured across a variety of metal stack and pad configuration options
- A 16nm/12nm Flip-Chip IO library with dynamically switchable 1.8V/3.3V GPIO, 5V I2C open-drain, 5V OTP and 1.8V / 3.3V analog
- A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- A 180nm Flip-Chip IO library with 1.2-1.8V GPIO, 1.8V & 5V analog/RF, 20-36V ultra-low leakage low-cap HV analog and OTP program cell
- A 65nm Wirebond IO library with 2.5V GPIO, LVDS TX & RX and 2.5V analog / RF