The CCP2 transmitter consists of a 32:1 serializer followed by LVDS drivers for transmitting clock (or strobe) and data. The LVDS drivers operate in subLVDS mode only, which is defined in the CCP2 standard. Each LVDS driver has a programmable on-die termination resistor to facilitate high frequency operation, and supports test data output mode. The LSB of 32-bit data is sent first. The clock for the serializer is generated using a local PLL. The maximum data rate for the transmitter is 960Mb/s.
- High speed subLVDS data/clock or data/strobe signaling
- Internal PLL for high speed clock generation
- Programmable on-die termination resistors
- Power down mode
- Built-in test pattern generation
- Full industrial operating temperature range -40 ~ +125°
- SMIC 0.13um Logic Salicide Process (1P6M, 1.2V/2.5V)