The FFT4096 core the FFT and IFFT computations for N input samples, where N can be any power of 2 between 32 and 4096 (32, 64, 128,...…4096), in hardware with very low latencies. The core also supports 2N-point real time samples to complex symmetric frequency samples FFT and N complex symmetric frequency samples to 2N time domain real samples IFFT.
- Supports 32/64/128/256/512/1024/2048/4096 point complex FFT and IFFT and up to 8192 point real-to-complex and complex-to-real FFT and IFFT and can switch dynamically. The real-to-complex and complex-to-real FFT/IFFT does not require any additional memory.
- Built-in bit reversal. Outputs in natural order
- Supports reading output data in any order (read address)
- Low Latency. Can be customized to improve latency vs. gate count
- Throughput of 1 sample per clock
- Parameterized bit widths and fixed-point option.
- Test bench with fixed-point Matlab and optional C++ models
- Available in ASIC and FPGA technologies
- Minimal gate count implementation
- Supports flushing and re-starting of the FFT operation instantly
- Configurable bit width based on SQNR requirement for random inputs or for a specific stimuli pattern.
- Customization for OFDM applications