Intra-Panel Multi Strandard TX on Samsung Foundry LN08LPP/LPU
32 bit - Compact RISC-V Processor Core
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L10 and to generate corresponding hardware and software development kits.
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Block Diagram of the 32 bit - Compact RISC-V Processor Core
Processor IP
- RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- RT-660 DPA & Fault Injection Resistant Hardware Root of Trust Security Processor for Govt/Aero/Defense FIPS-140
- RT-660-FPGA DPA-Resistant Hardware Root-of-Trust Security Processor for Govt/Aero/Defense FIPS-140
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Secure-IC Securyzr(TM) Cyber Escort Unit IP provides real time detection of sero day attacks on processor
- 64-bit RISC-V Application Processor Core