The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient 32-bit embedded processor IP core implementing the RISC-V Instruction Set Architecture (ISA).
The Harvard architecture EMSA5 processor implements a single-issue, in-order, 5-stage execution pipeline, supporting the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E). EMSA5 can support machine and user privilege modes, and optionally the standard Multiply (M), Compressed (C), Control and Status Register (Zicsr), and Instruction-Fence (Zifencei) RISC‐V extensions. The processor core communicates with the system via two 32-bit AHB-lite buses (one for data and one for instructions) and its interrupt lines.
Designed to meet the most stringent functional safety requirements, EMSA5-FS implements a memory protection unit, employs modular redundancy, uses error correction codes (ECC), and is delivered with sample reset and safety manager modules. Privileged operation modes provide a mechanism to isolate application user-mode processes from each other and from trusted code running in machine mode. The highly configurable memory protection unit enables memory partitioning, which provides protection by restricting access or specific types of access to memory and memory-mapped modules (e.g. peripherals). ECC protects the memories and buses and modular redundancy protects the internal processor modules. Finally, the safety manager provides logical and timing supervision and can be customized to meet the requirements of the end application.
Part of CAST’s family of processor cores, the EMSA5-FS processor core has been designed for easy reuse, has been rigorously verified, and is delivered with an ISO 26262 ASIL-D Ready certificate.