Camera SLVS-EC v.2.0 5.0Gbps / MIPI D-PHY v2-1 4.5Gbps combo Receiver 4-Lane
32-bit High Performance Single/Multicore RISC System-on-Chip with code compression
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Block Diagram of the 32-bit High Performance Single/Multicore RISC System-on-Chip with code compression
SoC IP
- Ultra low power AI inference accelerator
- Root of Trust eSecure module for SoC security
- Tessent SoC debug and optimization
- RT-630 Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- RT-630-FPGA Hardware Root of Trust Security Processor for Cloud/AI/ML SoC FIPS-140