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32-bit RISC CPU ComHigh performance 32-bit RISC CPU with two instructions running simultaneouslypatible with object code level with SH-1, SH-2, and SH-3
SH - 2A is a high - performance 32 - bit RISC CPU with two instructions running simultaneously.
Features
- 32 bit internal data bus
- General-purpose register architecture: 16 32-bit general-purpose registers
- Register bank for fast interrupt response (15 banks)
- RISC type instruction set: Instruction length: 16 bits / 32 bits mixed, 16-bit basic instruction for improving code efficiency, 32-bit instruction for improving performance and usability
- Two instructions simultaneous execution superscalar
- Instruction execution time: Up to 2 instructions / cycle
- Address space: 4 Gbytes, big endian
- 5 stage pipeline
- Harvard architecture
- Peripheral circuit
- Cache, URAM, H-UDI, UBC, Peripheral IOs, DMAC, BUS
Block Diagram of the 32-bit RISC CPU ComHigh performance 32-bit RISC CPU with two instructions running simultaneouslypatible with object code level with SH-1, SH-2, and SH-3
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32-bit RISC CPU
- Compact, low-power 32-bit RISC CPU
- High-performance 32-bit RISC CPU
- RISC-V Processor - RV12 - 32/64 bit, Single Core CPU
- Ultra Compact 32-bit RISC-V CPU Core
- Vector Floating-point coprocessor based on ARM VFPv2 Instruction Set Architecture for FA626TE 32-bit RISC CPU
- 32-bit RISC CPU interpreting and executing the SH-DSP instruction that extended the SH 2 instruction