32-bit RISC-V core with in-order pipeline

Features

• Architecture: RV32IMACF
• 32-bit RISC-V with 32 integer registers (I extension)
• Integer multiplication and division (M extension)
• Atomic operation support (A extension)
• Compressed mode for better code density (C extension)
• Optional IEEE 754-2008 compliant single precision floating point (F extension)
• Single instruction issue
• Machine, Supervisor and User modes
• 10 stage in-order pipeline
• Advanced branch predictor: BTB, BHT, RAS
• Sv32 Virtual Memory support
• 4 to 32 KiB, 2 to 8-way L1 I-cache
• 4 to 32 KiB, 2 to 8-way L1 D-cache
• Integrated 128 KiB to 2 MiB L2 Cache
• Interrupts
• Platform Level Interrupt Controller (PLIC): 127 interrupts with 8 priority levels
• Multi-Core Local Interruptor (CLINT): timer + software interrupts
• Integrated debug controller
• AXI system interface
• AXI peripheral interface
• AXI front-port interface for peripherial coherent access
• Performance
• 1.6 DMIPS/MHz
• 2.9 CoreMark/MHz
• Frequency
• 1 GHz (TSMC, 40nm G, SSG corner)
• 1.2 GHz (TSMC, 28nm HPC+, SSG corner)

Block Diagram of the 32-bit RISC-V core with in-order pipeline

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