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320Gbps Ethernet Switch
Packet Architects offers a series of high speed switching IPs which are developed using the unique FlexSwitch toolchain. The toolchain allows a fast and flexible development of switching/routing IP for any packet based technology.
This L2 Ethernet Switching IP offers a full range of features with full wirespeed on all ports plus a high speed CPU port. Each port has priority queues which are controlled by a strict priority scheduler allowing the most timing critical packets to get minimal delay while providing a fairness between queues. The switching core is built around a shared buffer memory architecture allowing head of line blocking free switching on all ports operating at wirespeed. It offers dynamic per port and per priority usage of the packet buffer memory along with buffer limiters to limit how much an egress port / priority uses of total buffer memory. The switching core also features multiple VLAN tagging and untagging along with egress VLAN translation.
The L2 Ethernet Switching IP features a processor interface allowing setup of tables and register. It also features a packet based CPU port which can be used to both send and receive ethernet frames to/from the switching IP.
This IP requires no software setup to be used, it is ready to receive and forward Ethernet frames once downloaded to FPGA and connected to MACs. It has hardware learning for MAC addresses.
This L2 Ethernet Switching IP offers a full range of features with full wirespeed on all ports plus a high speed CPU port. Each port has priority queues which are controlled by a strict priority scheduler allowing the most timing critical packets to get minimal delay while providing a fairness between queues. The switching core is built around a shared buffer memory architecture allowing head of line blocking free switching on all ports operating at wirespeed. It offers dynamic per port and per priority usage of the packet buffer memory along with buffer limiters to limit how much an egress port / priority uses of total buffer memory. The switching core also features multiple VLAN tagging and untagging along with egress VLAN translation.
The L2 Ethernet Switching IP features a processor interface allowing setup of tables and register. It also features a packet based CPU port which can be used to both send and receive ethernet frames to/from the switching IP.
This IP requires no software setup to be used, it is ready to receive and forward Ethernet frames once downloaded to FPGA and connected to MACs. It has hardware learning for MAC addresses.
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Block Diagram of the 320Gbps Ethernet Switch IP Core
