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32G Multi-protocol SerDes PHY
The 32 Gbps Multi-protocol SerDes PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure applications.
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Block Diagram of the 32G Multi-protocol SerDes PHY IP Core
Serdes IP
- 250Mbps to 12.7Gbps Multiprotocol SerDes PMA
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- 250Mbps to 8.1Gbps Multiprotocol SerDes Wirebond PMA
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP