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RT-630-FPGA Programmable Root-of-Trust Security Processor for Cloud/AI/ML SoC FIPS-140
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32G Multi-protocol SerDes PHY
The 32 Gbps Multi-protocol SerDes PHY is designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G infrastructure applications.
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Block Diagram of the 32G Multi-protocol SerDes PHY IP Core
Serdes IP
- PCIe 5.0 SerDes PHY
- 1-64Gbps PCI-Express Gen1 - Gen6 PHY and CXL SerDes
- 1-112Gbps Medium Reach (MR) and Very Short Reach (VSR) SerDes
- 250Mbps to 16Gbps Multiprotocol SerDes PMA
- 250Mbps to 8.1Gbps Multiprotocol SerDes Wirebond PMA
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)