Extoll’s SerDes architecture is based on digital design elements and methodologies. Plain analog blocks are only used where absolutely necessary. Various digital control and tuning loops are employed to achieve robust performance across process and operating conditions. This allows a maximum of flexibility and reduces the effort for migration to alternate target technologies. The design itself is complemented by the comprehensive advanced verification and modeling methodology employed by Extoll.
A single SerDes PHY block can consist of up to 4 bidirectional lanes and one common PLL that can be driven at various input reference clock frequencies to achieve line rates ranging from 1.25 to 32Gbps. Multiple PHY blocks can be combined to construct wider links.Moreover, the PHY IP can be adapted to custom requirements easily.
The IP enables the smallest footprint of a multi rate multi protocol and long reach SerDes Interface in the industry with lowest power consumption and channel support of up to 12 dB insertion loss for very short reach applications.
Extoll´s SerDes is best suited to support high-speed data applications in Industrial, Aerospace, Automotive, HPC and QC segments.