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Compact, efficient 64-bit RISC-V processor with 5-stage pipeline
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33G Die-to-Die SerDes PHY (12nm 16nm)
The AnalogX AXDieIO IP utilizes the silicon-proven AXLinkIO transceiver architecture for die-to-die, in package, type of channel links.
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Block Diagram of the 33G Die-to-Die SerDes PHY (12nm 16nm)
