The S3BUF350MT40LP is a Low-power Single-ended to Differential ADC Driver. The block has a 1.0Vpp single ended Input range, a Differential Output of 1.0Vppd and a -3dB bandwidth of 350MHz.
The S3BUF350MT40LP has excellent dynamic performance including -55.0dB THD, and an input referred Noise of 7.6nV/√Hz @ 10MHz.
The S3BUF350MT40LP has a high input impedance and a typical power dissipation of 87.5mW.
The S3BUF350MT40LP is designed to drive the S3ADS320M12BT40LPB ADC.
The S3BUF350MT40LP uses Deep N-Well for superior noise isolation. It can be cost-effectively ported across foundries and process nodes upon request.
- TSMC 40nm LP (Low Power Process)
- Analog Options: Deep N-Well
- 1.1V Core & 2.5V I/O Supplies
- -3dB Bandwidth: 350MHz
- Single-ended Input Signal Range: 1.0Vpp
- Differential Output: 1Vppd
- High Impedance Input
- Low input referred Noise: 7.6nV/√Hz @ 10MHz
- Programmable Internal Reference Voltage
- Outstanding Dynamic Performance:
- 0.178% THD / -55dB @10MHz
- Power-Down Mode
- Low Power Dissipation
- Small Area
- Capable of directly handling Video inputs
- High Performance.
- Low Power
- Low Area
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
- Video Acquisition/
- General purpose Single Ended to Differential Conversion
Block Diagram of the 350MHz Single-ended to Differential ADC Buffer