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MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
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3GPP LTE UL Channel Decoder
The 3GPP LTE Channel Decoder provides a high-performance, optimized decode function for the Uplink Shared Channel (UL-SCH), as defined in 3GPP. Core Generator options allow the user to generate underlying transport block and channel quality information decode chains, supporting applications such as relay nodes. The 3GPP LTE Channel Decoder is a component in Xilinx LTE Baseband Targeted Design Platform.
Features
- Uplink Shared Channel decoder for 3GPP TS 36.212 v9.3.0
- Transport Block Decoder and Channel Quality Information Decoder sub-components can be Generated as stand-alone cores
- TDD/FDD compliant
- Support for on or off chip codeword buffering
- Integrated descrambling
- Integrated LLR calculation
- Fully decoupled decoding chains
- Fully optimized for speed and area
- Fully synchronous design using a single clock
- Bit Accurate C model
- Customer demonstration test bench
View 3GPP LTE UL Channel Decoder full description to...
- see the entire 3GPP LTE UL Channel Decoder datasheet
- get in contact with 3GPP LTE UL Channel Decoder Supplier
Communications
- CPU Designed for the Next Generation of High Performance Wireless Communications and Networking
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