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4.3 GHz Integer PLL (71103)
This is a dual supply voltage integer Phase Locked Loop (PLL). It generates an output clock which is determined by a 6-bit pre-divider, 10-bit main-divider and 3-bit scaler. The input clock bypass mode, lock detection and glitch-free function are available.
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Block Diagram of the 4.3 GHz Integer PLL (71103) IP Core
