You are here:

4.3 GHz Integer PLL (71103)

This is a dual supply voltage integer Phase Locked Loop (PLL). It generates an output clock which is determined by a 6-bit pre-divider, 10-bit main-divider and 3-bit scaler. The input clock bypass mode, lock detection and glitch-free function are available.

Features

14nm Low Power CMOS device technology
1.8V, 0.9V to 0.8V dual power supply
Operation junction temperature: -40 to 125°C
Input frequency range: 4MHz to 300MHz
Output frequency range: 33.6MHz to 4.3GHz
Period Jitter: ±1.5% of VCO clock period , FVCO ≤ 3GHz ± (0.75% of VCO clock period + 2.5ps), FVCO > 3GHz
Output clock duty ratio: 45 to 55%
Glitch-free scaler / Lock detector/ Input bypass mode (FOUT=FIN)

Deliverables

Data Sheet
User Guide
Verilog model
Timing LIB
CDL netlist
Layout (GDSII or OAS)

Applications

Mobile/Consumer/IoT

Block Diagram of the 4.3 GHz Integer PLL (71103) IP Core

4.3 GHz Integer PLL (71103) Block Diagam

View 4.3 GHz Integer PLL (71103) full description to...

see the entire 4.3 GHz Integer PLL (71103) datasheet
get in contact with 4.3 GHz Integer PLL (71103) Supplier

integer pll IP

See more integer pll IP >>

No portion of this site may be copied, retransmitted, reposted, duplicated or otherwise used without the express written permission of Design And Reuse.