4 channel SERDES
Depending on the application, each transmitter can serialize 8, 10, 16 or 20 bit parallel data to a differential serial output and each receiver can de-serialize a differential serial input to 8, 10, 16 or 20 bit parallel output. A common block including a TXPLL provides clocks to the serializers in all channels. To improve signal integrity the common block also includes a calibration circuit providing control signals to make the transmitter output resistance and the receiver input resistance within 50Ω±10%.
Fig 3. Shows the block diagram of each channel. At the RX side the serial input data goes through the input stage with linear equalization. The Clock and data recovery (CDR) circuit receives the data. It then extracts the clock, and provides the clock and the retimed data to the de-serializer. The de-serializer converts the serial data to 8, 10, 16 or 20bit parallel data with corresponding rx-clk.
There is an eye-monitor block to measure the height of the signal going to the CDR. When enabled, the information about the height of the signal will be sent out through 16 bit parallel data line.
A Loss Of Signal (LOS) detector also detects if there are valid data at the input.
For the boundary scan testing there is a AC JTAG block at the input providing data to the core in the test mode. At the TX side the serialized data goes through the output driver. To further improve the jitter performance there are programmable pre-emphasis capabilities at the transmitter output stage.
In addition near end and far end serial loopback are implemented to be able to test the channel.
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