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4-GHz Jitter-optimized low-power digital PLL
Perceptia’s DeepSubTM pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV post-scaler. pPLL03 is currently in silicon in the Silterra 180G, ON Semi 180, GlobalFoundries 65LPe, and TSMC 65LP processes.
Features
- - Jitter below 10-ps
- - Super small: 90 x 90 microns!
- - Very low power: 15-mW
- - Broad frequency range: 4-GHz
- - Fast lock
- - Lock detect
- - Preprogrammed loop filter
- - BIST
- - Scan testable
- - Power-down mode
- - Decoupling caps for lower jitter
- - Available with companion LDO regulator IP
Deliverables
- The pPLL03 series PLL macros are delivered with:
- - Detailed datasheet including guidance for layout, packaging and production test
- - Characterization report or post-layout corner simulation report
- - LEF abstract for floor planning/chip assembly
- - GDSII layout macrocell
- - Spice/CDL netlist (encrypted format) for LVS
- - DRC / SI verification report
- - Verilog model
- - Timing model (.lib)
- - Test vectors and test guidelines
- - Integration support
Block Diagram of the 4-GHz Jitter-optimized low-power digital PLL IP Core
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PLL
- MIPI D-PHY 1.5Gbps (4-lanes TX/RX, PLL Integrated) TSMC 28HPM
- MIPI D-PHY 2.0Gbps (4-lanes TX/RX, PLL integrated) TSMC 16FF+LL
- MIPI D-PHY 2.0Gbps (4-lanes TX, PLL integrated) TSMC 16FF+LL
- TSMC CLN7FFLVT 7nm Deskew PLL - 300MHz-1500MHz
- TSMC CLN7FF 7nm Spread Spectrum PLL - 700MHz-3500MHz
- Ultra-Low-jitter Ring PLL