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4-GHz Jitter-optimized low-power digital PLL

Perceptia’s DeepSubTM pPLL03 series PLLs are low-cost low-power low-jitter PLLs, for foundry processes from 28 to 180-nm. They are typically used together with the companion IPs pREG01 regulator and pDIV post-scaler. pPLL03 is currently in silicon in the Silterra 180G, ON Semi 180, GlobalFoundries 65LPe, and TSMC 65LP processes.

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Block Diagram of the 4-GHz Jitter-optimized low-power digital PLL IP Core

4-GHz Jitter-optimized low-power digital PLL Block Diagam

PLL IP

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4-GHz Jitter-optimized low-power digital PLL

View 4-GHz Jitter-optimized low-power digital PLL full description to...

Block Diagram of the 4-GHz Jitter-optimized low-power digital PLL IP Core

PLL IP

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