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4-lane MIPI CSI2 serial video transmitter for FPGA implementations
Compact serial video tranmitter comlying with MIPI CSI2 standrad, supporting from 1 to 4 data lanes and optimized for FPGA implementatons
Features
- The SVT-CS4AP1-F supports MIPI CSI2 over MIPI D-PHY.
- Functionality highlights include:
- One clock lane, and one to 4 data lanes
- Up to 1.5Gbps per lane;
- Supports CSI2 RAW8, RAW10, RAW12, all YUV420, all YUV422 and User-Defined 8-bit formats (other CSI2 standards available as an option).
- CRC and ECC generation
- Programmable timing parameters
- The SVT-CS4AP1-F is optimized for FPGA Implementations
Deliverables
- Verilog RTL, Programmer Reference Manual, Support
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MIPI CSI2 FPGA
- MIPI D-PHY Compliant With CSI-2 And DSI
- MIPI D-PHY TSMC 130nm
- MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
- MIPI CSI-2 RX Controller Subsystem
- MIPI D-PHY Digital Front-End for FPGA
- Camera Sensor Receiver Interface Converting from MIPI CSI-2 to AXI4-Stream Video Standard