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400GE PCS
The Precise-ITC CDPCS IP core is a cutting edge solution to the 400G Ethernet application. It supports the Physical Coding Sublayer (PCS) for 64B/66B, type 400GBASE-R function based on the IEEE 802.3bs-2017.
The CDPCS supports 64B/66B encoding for transmission of data and control characters, 256/257B transcoding, FEC calculation, and data distribution to support multiple lanes in the Physical Layer. It includes insertion and extraction points for connection to an OTN layer. This core is suitable for use in switch or interface cards or any application that requires a PCS for 400GbE. All functions of the CDPCS are compliant with the IEEE 802.3bs. For a complete Ethernet solution, the CDPCS seamlessly integrates with the Precise-ITC 400G MAC (CDMAC) core.
The CDPCS supports 64B/66B encoding for transmission of data and control characters, 256/257B transcoding, FEC calculation, and data distribution to support multiple lanes in the Physical Layer. It includes insertion and extraction points for connection to an OTN layer. This core is suitable for use in switch or interface cards or any application that requires a PCS for 400GbE. All functions of the CDPCS are compliant with the IEEE 802.3bs. For a complete Ethernet solution, the CDPCS seamlessly integrates with the Precise-ITC 400G MAC (CDMAC) core.
Features
- CDPCS TX
- 64B/66B encoding of twenty input lanes
- Idle block removal (to reduce overhead for AM insertion)
- 256/257B transcoding (to reduce overhead for FEC insertion)
- Scrambling (optional bypass)
- Alignment Marker (AM) insertion. Unique marker portion of AM for each lane is s/w configurable.
- Forward Error Correction (FEC) parity calculation and insertion (2x200G interleaved)
- Symbol Distribution so that output is composed of 16 lane of 80-bits (version F) or 40-bits (version A) each
- Test pattern generation (scrambled idles)
- Clause 45 MDIO register set
- Error detection and interrupt reporting
- CDPCS RX
- Alignment lock and lane deskew of 16 lanes. Unique marker portion of AM for each lane is s/w configurable
- Lane reordering
- FEC decoding and error correction (2x200G interleaved)
- Alignment marker removal
- Descrambling (optional bypass)
- Reverse 256/257B transcoding
- 64B/66B decoding to twenty output lanes
- Test pattern monitoring
- Clause 45 MDIO register set
- Error detection and interrupt reporting
- Loopback from TX CDMII to RX CDMII
- Performance Monitoring and Statistics
- Dynamic skew measurement for each lane
- FEC Corrected code word count
- FEC Uncorrected code word count
- FEC symbol error counter
- PCS Status – link up/down
- High bit error rate (hi-BER)
- BER counter
- Test pattern error counter
- Multi-lane AM status (locked and aligned/not locked and aligned)
- Lane mapping for each of physical lanes 0-15
Block Diagram of the 400GE PCS IP Core
View 400GE PCS full description to...
- see the entire 400GE PCS datasheet
- get in contact with 400GE PCS Supplier