The Xelic XCO23EFEC7 I.7 Enhanced Forward Error Correction (EFEC) Core performs FEC encoding and decoding for either 1 OTU3 or 4 independent OTU2 streams. The XCO23EFEC7 contains independent encoder and decoder functions which utilize two orthogonally concatenated BCH codes, providing a standard 7 percent parity overhead solution. The XCO23EFEC7 implements the G975.1.I.7 specification and has been through extensive interoperability testing with other implementations. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU3 rate using a 128-bit data bus operating at 334.66MHz. This core can be used in place of 1 40G core and 4 10G cores and is a fraction of the size.