The Xelic XCO23EFEC7 I.7 Enhanced Forward Error Correction (EFEC) Core performs FEC encoding and decoding for either 1 OTU3 or 4 independent OTU2 streams. The XCO23EFEC7 contains independent encoder and decoder functions which utilize two orthogonally concatenated BCH codes, providing a standard 7 percent parity overhead solution. The XCO23EFEC7 implements the G975.1.I.7 specification and has been through extensive interoperability testing with other implementations. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU3 rate using a 128-bit data bus operating at 334.66MHz. This core can be used in place of 1 40G core and 4 10G cores and is a fraction of the size.
- Optimized for ASIC implementations.
- Integration support and maintenance available.
- XCO23EFEC7 core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.975.1 Amendment I.7 specification.
- Standard 7 percent parity overhead.
- Encoder includes single bit error insertion for diagnostic purposes.
- Decoder includes five iterative stages of BCH error correction, Row1 Col1 Row2 Col2 Row3.
- Each decode stage can be disabled under via input control signals.
- Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
- Provides uncorrected codeword outputs.
- Provides status outputs for internal MSYNC state machine.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Provides a single-bit error insertion capability.
- Overall latency of 35us for 40G ports, 140us for 10G ports.
- OTU2, OTU3 line cards
- Test equipment