40G G975.1 I.4 Enhanced FEC Core
Features
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO3EFEC4 core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.975.1 Amendment I.4 specification.
- Encoder includes single bit error insertion for diagnostic purposes.
- Decoder includes four iterative stages of error correction, BCH1 RS1 BCH2 RS2.
- Each decode stage can be disabled via input control signals.
- Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values.
- Provides uncorrected codeword outputs.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Provides a single-bit error insertion capability
- Overall latency of 16us.
Applications
- OTN/SONET add/drop multiplexer
- OTN switch
- Digital cross connects
- OTN and/or SONET/SDH line cards
- Test equipment
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