The Xelic 40Gb/s I.7 Enhanced Forward Error Correction (EFEC) Core (XCO3EFEC7) generates codeword parity bits and performs error detection and correction for OTU3 data streams. The XCO3EFEC7 contains independent encoder and decoder functions which utilize two orthogonally concatenated BCH codes, providing a standard 7 percent parity overhead solution. The XCO3EFEC7 implements the G975.1.I.7 specification and has been through extensive interoperability testing with other implementations. Corrected and Uncorrected codeword detection is provided along with configurable High BER status information. Line and system side data is transferred at an OTU3 rate using a 128-bit data bus operating at 334.66MHz.