MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
40G OTN Digital Wrapper
Description
In the source direction data is transferred from the client clock to the line clock for ODU/OTU frame generation through an asynchronous fifo. The frame timing generator block generates row and column counts and alignment pulses to synchronize payload mapping, overhead insertion, FEC encoding and scrambling. The OPU Mapper block maps the input data into the OPU payload and calculates the overhead bytes and maps them into the overhead region with BMP or AMP. The ODU_OTU Overhead Generator (ODU_OTU OH Gen) block generates all overhead fields. OH bytes are received over an external OH insert interface bus. Maintenance signals are generated as consequent actions from defects detected by the sink direction and are inserted by the OH overwrite block. The OH overwrite block can overwrite any OTU/ODU/OPU overhead byte with software configured values. FEC insertion is optionally inserted from an external FEC encoding interface. The OTUk frame is then scrambled before sending to the line interface.
In the sink direction, line data is aligned by the Framer based on a programmable FAS. The framer generates row and column counts and alignment pulses to synchronize subsequent modules for performing descrambling, FEC decoding and extraction of overhead and payload data. The OTUk frame is then de-scrambled and passed to an optional FEC module which interfaces to an external FEC processor. The OTU_ODU overhead processor (OTU_ODU OH Processor) block extracts overhead bytes for processing by software. Overhead bytes are stored in the OH capture RAM for access by software. Alarms are processed. The OPU demapper block extracts payload data and OPUk overhead information if AMP mapped. The OPU overhead bytes are stored in the OH capture RAM and are optionally sent to an OH extract interface for external processing. Data is passed through an asynchronous fifo for transfer to the client on a client clock.
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