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40GBASE-R PCS
The 40GBASE-R Physical Coding Sublayer (PCSXL) module provides the functionality of a physical coding sublayer (PCS) on data being transferred between XLGMII and SerDes modules supporting a 16 bit or 32 bit interface.
Features
- 40 Gigabit Ethernet specific PCS between a 40 Gigabit Ethernet MAC (XLGM) and four 10 Gigabit SerDes modules supporting a 16- or 32-bit interface
- Features as per IEEE 802.3ba Clause 82:
- XLGMII interface
- 64/66B encoding and decoding
- Data scrambler on transmit path and descrambler on receive path
- Alignment marker insertion on transmit path and alignment maker removal on receive path
- Clock tolerance compensation on receive path
- Internal loopback mode
- Optional MDIO interface
- PRBS31 pattern generator and error checker
- PRBS9 pattern generator and error checker
- Optional support for Forward Error Correction (FEC) sub-layer for 40GBASE-R PHYs
Deliverables
- Synthesizable Verilog RTL
- Verilog testbench and scenarios
- Synthesis scripts
- User documentation
View 40GBASE-R PCS full description to...
- see the entire 40GBASE-R PCS datasheet
- get in contact with 40GBASE-R PCS Supplier