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USB-C 3.1 SS/SSP PHY, Type-C - TSMC 16FF+LL, North/South Poly Orientation
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40nm Low Leakage VHS, Channel Length 40nm, RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage VHS, channel length 40nm, RVT Logic Process Standard cell Library
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Standard Cell
- DesignWare HPC Design Kit contains high-speed and high-density memory instances and standard cell libraries
- 10 track thick oxide standard cell library at TSMC 55 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
- 8 track thick oxide standard cell library at TSMC 90 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
- 7 track Ultra High Density standard cell library at TSMC 28 nm
- 10 track thick oxide standard cell library at GF 55 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
- 6 track Ultra High Density standard cell library at TSMC 55 nm