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PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
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40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage
40nm LP DDR3/4 LPDDR23 COMBO PHY DATA Block for Flip Chip usage
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Interface Solution IP
- Compute Express Link (CXL) 2.0 Controller with AMBA AXI interface
- PCIe 6.1 Controller
- PCIe 5.0 Controller with AMBA AXI interface
- CCIX 1.1 Controller with AMBA AXI interface
- PCIe 4.0 Controller with AMBA AXI interface
- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface