The LTE/LTE-A IP Core is an advanced, customer-proven implementation of the standardized 3GPP turbo code.
LTE and LTE Advanced (LTE-A) are the mobile broadband standard of the 4th generation. Current LTE installtion provides datarates up to 300 Mbit/s. LTE-A increase the throughput up tp 1 Gbit/s.
- Support for 3GPP Release 8 LTE turbo decoding
- Support for 3GPP Release 10 LTE Advanced turbo decoding
- Support for codewort CRC and up to four transport block CRCs
- Soft information output available
- Throughput up to 1 Gbit/s.
- Design-time configuration of input quantization.
- Configurable amount of turbo decoder iterations for trading-off throughput and error correction performance.
- Available for ASIC and FPGAs (Xilinx, Altera).
- Deliverable includes VHDL source code or synthesized netlist, VHDL or SystemC testbench, and bit-accurate Matlab, C or C++ simulation model.
- An IP core may contain the following elements:
- Hardware model as netlist for Xilinx or Altera FPGAs
- Hardware model as VHDL source code
- Bit-accurate software reference model as pre-compiled library for Linux or Windows. You can easily integrate this model into your Matlab, C or C++ environment.
- Test environment for the hardware of the IP core consisting of VHDL testbench and test data as well as post-synthesis simulation model or pre-compiled simulation model.
- Delivery will be made either by download from our FTP server or by encrypted email.
- LTE/LTE-A modem chipset for base station (BS) or user equipment (UE)
- Applications with highest demands on forward error correction
- Applications with the need for a wide range of code rates and block lengths