4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder
ParaQum HEVC decoder is world's first 4K real time HEVC decoder implemented on an FPGA with sub 150MHz clock frequencies.
High Efficiency Video coding (H.265) is the emerging video compression standard that promises 50% bit rate reduction compared to its predecessor H264. This IP core takes HEVC compliant elementary streams and outputs raw video. The decoder interfaces are AXI compliant for easy integration.
View 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder full description to...
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Block Diagram of the 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder IP Core
Video Demo of the 4K, 4:2:0/4:2:2:/4:4:4, 8/10/12 bit HEVC Decoder IP Core
This video demonstrates real time decoding of 4K 30fps using Paragon HEVC decoder on Xilinx Zynq ZC 706 FPGA. Paragon HEVC decoder is capable of decoding 4K videos up to 45 fps and supports bit depths up to 12.
4:2:0 , 4:2:2 and 4:4:4 profiles are supported in Paragon HEVC decoder
HEVC Decoder IP
- 4K/ 8K LCEVC Video Decoder
- HEVC/H.265 + AVC/H.264 Decoder IP Single-CORE for 4Kp60
- Multi-format decoder for 4K UHD with a single-core, 4:2:0 10-bit (max 8K). HEVC/H.265, AVC/H.264, VP9, AV1 and AVS2
- HEVC/H.265 and VP9 Multi format Decoder for UHD(up to 8K) 4:2:0 10bit
- 1080p60 Multi-Format Decoder IP
- HEVC/AVC Single-core Video Codec HW IP: 4K60fps