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4x10Gbps / 1x40Gbps OTN Enhanced FEC IP Core
The XCO23EFEC47 is an ITU-T G.975.1 Appendix I.4 and I.7 compliant Super FEC Encoder and Decoder pair. Both ITU-T G709 I.4 and I.7 compliant scheme provides a higher coding gain than the standard RS(255, 239) for gaussian error distributions while maintaining the standard 7 (16:239) parity:data overhead.
This core can be programmed for 4x10G, 40G OTU3 or 40G OTL3.4 operation and is intended for use with one XCO3 40G Digital Wrapper OTN Framer Core or with four XCO2 10G Digital Wrapper OTN Framer Core. In 4x10G mode, the XCO23EFEC47 codec can process 4 channels of ODU2 and each channel is programmed to be 32-bit wide and operates at a rate of OTU2/32. The XCO23EFEC47 decoder performs bit correction in each individual channel and provides the statistical counts for each channel. Each channel can be independently programmed to perform I.4 or I.7 algorithm. In 40G mode, The XCO23EFEC47 codec can process 1 channel of ODU3 and the channel is programmed to be 128-bit wide and operates at a rate of OTU3/128. The XCO23EFEC47 decoder performs bit correction and provides the statistical counts for both OTU3 data stream as well as OTL3.4.
This core can be programmed for 4x10G, 40G OTU3 or 40G OTL3.4 operation and is intended for use with one XCO3 40G Digital Wrapper OTN Framer Core or with four XCO2 10G Digital Wrapper OTN Framer Core. In 4x10G mode, the XCO23EFEC47 codec can process 4 channels of ODU2 and each channel is programmed to be 32-bit wide and operates at a rate of OTU2/32. The XCO23EFEC47 decoder performs bit correction in each individual channel and provides the statistical counts for each channel. Each channel can be independently programmed to perform I.4 or I.7 algorithm. In 40G mode, The XCO23EFEC47 codec can process 1 channel of ODU3 and the channel is programmed to be 128-bit wide and operates at a rate of OTU3/128. The XCO23EFEC47 decoder performs bit correction and provides the statistical counts for both OTU3 data stream as well as OTL3.4.
Features
- Suitable for FPGA implementations.
- Integration support and maintenance available.
- XCO23EFEC47 core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.975.1 Amendment I.4 & I.7 specification.
- Decoder includes four iterative stages of error correction for I.4, BCH1 RS1 BCH2 RS2; and five iterative stages of error correction for I.7, Row1 Col1 Row2 - Col2 Row3.
- Each data stream can be disabled under via input control signals.
- Provides corrected ones and corrected zeroes outputs, embedded scrambler is used to give optic line values for I.4.
- Provides uncorrected codeword outputs for the last stage.
- Architecture facilitates RAM sharing with other FEC cores.
- Provides a configurable High BER alarm.
- Overall latency of X us.
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