Xilinx® offers the 50 Gigabit Reed-Solomon Forward Error Correction (RS-FEC) IP core for data center and enterprise applications. This core is designed to the 25G/50G Ethernet Consortium Schedule 3 specification and connects seamlessly to the Xilinx soft 50G Ethernet Subsystem IP on Virtex® UltraScale™, Virtex UltraScale+™, Kintex® UltraScale+, and Zynq® UltraScale+ devices.
- Low latency
- Accessible as an integrated feature in the 50G Ethernet Subsystem
- Configuration and status bus
- Selectable AXI4-Lite interface for status output
- ECC RAM option