The fully integrated Physical Coding Sublayer (PCS) and Media Access Controller (MAC) core for 50Gbps Ethernet applications are compliant with IEEE 802.3cd draft standard. The interface to the PMA supports either 2x 25Gbps or a single 50Gbps bi-directional, serial interface. The PCS sublayer includes encoding, transcoding, scrambling, FEC layer, and symbol distribution.
The north-bound interface from the MAC provides a configurable n x 64-bit system interface.
The southbound interface performs the mapping of transmitting and receiving data streams (at the PMA layer) to the on-chip SERDES. This core is responsible for channel alignment and KP4 FEC management. The PCS supports an interface for 50GBASE-CR or 50GBASE-KR.
- Logic and power efficient KP4 FEC engine with full warnings and alarms
- Integrated 64B/66B and 256B/257B encoder for area efficiency
- Built-in loopbacks and PRBS generators/ checkers for test and diagnostics
- Fully compatible with IEEE802.3 2015 and IEEE 802.3 Draft Standards
- Super low latency with minimized fixed and variable delay for network efficiency.
- Supports 1588v2 time stamps and full error handling
- Supports 802.3br express traffic and 802.1Qbb priority flow control (PFC)
- Proven IP reduces development time and risk
- Upgrade process as the standard evolves
- Supports both 50GBASE-KR and 50GBASE-CR PMD interfaces
- Support next-generation 56G PAM4 SerDes
- Support for 2-lane or single-lane SERDES interface
- Off-the-shelf, proven technology implementation in Altera and Xilinx FPGAs and ASIC SOC
- Tested and interoperability-proven against Spirent and Viavi test equipment