The S3REG5033T18 is a regulator circuit which has been designed to provide 1.8V with a load current of up to 50mA, having a low area.
The S3REG5033T18 is a regulator circuit that features an automatic feedback sensing option to maintain a constant regulated output voltage level. It has been designed to provide a stable output in both low-drop and high-drop operation, while maintaining minimum ripple on supply lines in the presence of large load current spikes inherent with switching loads.
The S3REG5033T18 has been designed to allow low-drop operation in a low area (the PMOS pass device has been scaled for a voltage drop of no less than 0.062mV). To achieve these goals, the S3REG5033T18 requires a 4.7pF external ceramic capacitor.
- 0.18um TSMC eLL Process, 6 Metals Used
- 3.0V Input Voltage
- 1.8V Output Voltage +-3%
- 50mA Load Current
- Die Area: 0.062 mm2
- Leakage: 10nA
- Power Down Mode
- The S3REG5033T18 uses 3.3V thick oxide devices from the 0.18um TSMC eLL Process. The circuit can be scaled for a range of load currents.
- The S3REG5033T18 is readily portable to any similar manufacturing process or can be customised for specific customer requirements.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
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Block Diagram of the 50mA Regulator IP Core