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Configurable PCI Express 3.0, 2.0, 1.1 Controller IP for ASIC/SoC
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55LL general VIA ROM compiler
55LL general VIA ROM compiler
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Memories
- 3GPP LTE 3GPP2 1xEV-DO Turbo Decoder with Ping Pong Input and Output Memories
- Silicon-proven, High Density and Low Power Static Random Access Memories
- FIFO Generator
- 65LL high speed two-port register file compiler with HVT bit cell.
- SMIC 0.13um high density 2-Port SRAM compiler
- Error Correction Checking (ECC) Core