Design & Reuse
Catalog of SIP Cores
System on Chip design resources

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,

55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,...