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56G Ethernet PHY in TSMC (16nm, 7nm)
The DesignWare 56G Ethernet PHY IP meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leadingedge design, analysis, simulation, and measurement techniques, the 56G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3 and OIF standards electrical specifications. The PHY is small in area, low in power consumption, and high in performance, supporting channel loss of 35dB and meeting the needs of chip-to-chip, chip-to-module (copper and optical), and copper backplane interconnects
The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and NonReturn-to-Zero (NRZ) signaling to deliver up to 400G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the DesignWare Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.
The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and NonReturn-to-Zero (NRZ) signaling to deliver up to 400G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and internal eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the DesignWare Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.
Features
- Optimized for performance, power and area
- Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
- Supports IEEE and OIF standards: IEEE 802.3cd, CEI-56G
- Physical coding sublayer (PCS) blocks for backchannel initialization with broad range of optional features Low jitter transmitter and receiver (dual loop clock and data recovery) clock architectures
- Multi-lane PHY shares a single clock and support core
- Supports both internal and external reference clock connections to the PHY
- Configurable transmitter and DSP-based receiver with analog-to-digital converter
- Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
- Contains embedded pseudo random bit sequencer (PRBS) for internal and external loopbacks
- Embedded bit error rate (BER) tester and internal eye monitor
Benefits
- Supports full-duplex 9.9 to 58Gbps data rates in 1, 2, and 4 lanes
- Enables 50G, 100G, 200G, 400G Ethernet interconnects for wired network infrastructure
- Supports IEEE 802.3 and OIF standards electrical specifications
- Meets the performance requirements of chip-to-chip, chip-to-module, and backplane interconnects DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
- Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
- High-performance receive equialization supports channel loss of 35dB
- Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature
- Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance
Deliverables
- Verilog models and test bench
- Protocol-specific test bench
- Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
- GDSII
- IP-XACT XML files with register details
- ATPG models
- IBIS-AMI models
- Documentation
Applications
- Hyperscale data center
- Enterprise and campus networks
- Cloud computing/networking
- Service provider networks
- Artificial intelligence and machine learning
Video Demo of the 56G Ethernet PHY in TSMC (16nm, 7nm)
This OFC 2019 video demo shows Synopsys’ 56G Ethernet PHY IP running across multiple 400G interconnects. The IP is capable of operating across backplanes and optical, copper cables in QSFP-DD, OSFP, and SFP-DD form factors, meeting the IEEE 802.3cd standard. Synopsys’ PHY enables designers to meet their reach and performance requirements of their next-generation 400G hyperscale data center SoCs
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