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56G PAM4 SerDes PHY - Samsung Foundry 10 nm LP
The Samsung Foundry 56G PAM4 SerDes PHY IP is a hard-macro PHY for the IEEE and OIF protocols. I/O pads and ESD structures are included with extensive BIST features such as loopbacks decrease the test time. It offers a cost-effective and low-power solution. It builds on silicon-proven designs that are in network applications.
Features
- Samsung Foundry 10 nm low-power CMOS device technology
- Supports a maximum LR channel loss of -35dB@14 GHz (ball-toball)
- Supports a maximum -50dB@14 GHz crosstalk
- Supports BIST feature capable of producing and checking PRBS7/13/31 random patterns
- High-performance DAC in TX side can express extremely fine voltage level
- Fine resolution of 7-bit and wide SFDR of 49dBc
- Scalable power consumption according to channel-loss
- Changeable via the number of FFE+DFE taps from 0 ~ 10
- Full adaptation and calibration to guarantee stable performance
- IP fully calibrates gain, offset, and skew of analog blocks by itself
- IP fully adapts to any channels and phase-locks in any situation
Deliverables
- Front-end DK: Timing LIB, Verilog model, and sample test bench
- Back-end DK: Physical view LEF, GDSII layout, DRC, and LVS
- Documentation: Datasheet and user guide
Block Diagram of the 56G PAM4 SerDes PHY - Samsung Foundry 10 nm LP
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