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56G SerDes Ethernet
56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero (NRZ) signaling is supported in the range of 5.0-30.0 Gbps using full, half, and quarter-rate modes. Either scrambled or block coded (for example, 8B/10B) data is supported for 5.0-12.5 Gbps in NRZ mode. However, scrambled data is required for data rates greater than 12.5 Gbps.
The 56G SerDes IP cores are intended for use as a chip-to-chip or a card-to-card connection mechanism.
The 56G SerDes IP cores are intended for use as a chip-to-chip or a card-to-card connection mechanism.
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56G IP
- 56G Serdes in 7nm bundled with PCie Gen 5 controller IP
- 56G Ethernet PHY in TSMC (16nm, 7nm)
- DesignWare 56G Ethernet PHY IP for TSMC 12FFC
- Synopsys 56G Ethernet PHY IP in 12FFC
- 400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
- PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency