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5G NR IP Platform for Smartphones and Broadband Connected Devices
PentaG™ is industry’s first 5G NR IP platform capable of meeting the extreme performance, low latency and strict power budget requirements of 3GPP 5G UE solution for eMBB devices. It leverages CEVA’s unique expertise in DSP and modem architecture from working with world-leading wireless chip and OEM vendors.
The PentaG™ architecture contains specialized scalar and vector DSP processors, co-processors, AI processor, accelerators, software and other essential IP blocks, in a highly configurable and modular architecture.
PentaG™ supports the full gamut of 5G eMBB use cases, including standalone (SA) and non-standalone (NSA), mmWave and sub-6 GHz. It also supports LTE-A Pro (Gigabit LTE) and legacy LTE and 3G technologies. The platform sustains an impressive bit-rate of more than 10Gbps and offers a scalable architecture to support all advanced wireless technologies such as Massive-MIMO, beamforming and complex link adaptation schemes.
PentaG™ offers an optimal tradeoff between hardware and software to meet the stringent power and area requirements of 5G eMBB use cases and yet retain full flexibility to guarantee 5G NR Rel 15 and Rel 16 future-proofness.
The PentaG™ architecture contains specialized scalar and vector DSP processors, co-processors, AI processor, accelerators, software and other essential IP blocks, in a highly configurable and modular architecture.
PentaG™ supports the full gamut of 5G eMBB use cases, including standalone (SA) and non-standalone (NSA), mmWave and sub-6 GHz. It also supports LTE-A Pro (Gigabit LTE) and legacy LTE and 3G technologies. The platform sustains an impressive bit-rate of more than 10Gbps and offers a scalable architecture to support all advanced wireless technologies such as Massive-MIMO, beamforming and complex link adaptation schemes.
PentaG™ offers an optimal tradeoff between hardware and software to meet the stringent power and area requirements of 5G eMBB use cases and yet retain full flexibility to guarantee 5G NR Rel 15 and Rel 16 future-proofness.
Features
- Software components:
- CEVA-XC4500 5G NR libraries
- PentaG AI 5G NR processor libraries
- Communication libraries for LTE-A / WCDMA / TD-SCDMA RAT
- DSP Libraries and RTOS
- Hardware components:
- Enhanced CEVA-XC4500 DSP with 5G ISA Extensions
- PentaG AI Processor
- PentaG Vector MAC Unit (VMU) Co-Processor
- Cluster of CEVA-X2 DSPs
- Optimized HW accelerator: Polar Decoder/Encoder, LDPC Decoder/Encoder, FFT/IFFT, L2$ Cache Controller
- HW and SW Development Kit:
- Simulation Tools
- FPGA development board
- SW drivers to shorten HW/SW integration on prototype modem RTL
Benefits
- Fully configurable IP platform for 5G NR and multi-mode RAT.
- Lets customers focus on system development and integration using 5G NR software libraries optimized for state-of-the-art hardware IP.
- Reduces 5G NR modem design time-to-market and lowers entry barriers
- Software upgradable and scalable to support future 5G NR releases in addition to LTE-A Pro and 3G
- Supports high-end eMBB use cases for sub-6GHz and mmWave with ultra-low latency
Block Diagram of the 5G NR IP Platform for Smartphones and Broadband Connected Devices
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5G
- USB 3.1 PHY (10G/5G) - TSMC 16FFC x1 OTG, North/South Poly Orientation
- USB 3.1 PHY (10G/5G) - TSMC 16FF+GL x1 OTG, North/South Poly Orientation
- USB 3.1 PHY (10G/5G) - TSMC 16FF+LL x1 OTG, North/South Poly Orientation
- High performance, energy efficient 6-issue, 64-mac vector DSP core targeted for 4G/5G advanced wireless terminal and Infrastructure applications with scalable vector processing based on the fourth generation ZSP architecture
- High performance, energy efficient 4-issue, 32-mac vector DSP core targeted for 4G/5G wireless terminal and Infrastructure applications with scalable vector processing based on the fourth generation ZSP architecture
- High performance, energy efficient 4-issue, 16-mac vector DSP core targeted for 4G/5G wireless terminal and Infrastructure applications with scalable vector processing based on the fourth generation ZSP architecture
