5G PHY IP for PCIe 2.0 (Silicon Proven in TSMC 55ULP / 65ULP)
The PCIe2.0 PHY IP transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high-data throughput. The PCIe2.0 PHY IP comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, built-in self test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs
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pcie2.0ip IP
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- Quad Lane 5Gbps PCIe 2.0 PHY IP (Silicon Proven in TSMC 22ULP/ULL)
- PCIe Gen2 PHY IP (Silicon Proven in SMIC 40LL)
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