The LDPC decoder receives samples from the QAM demapper. The number of input samples read per clock-cycle may be varied from packet to packet, typically as a function of the number of bits in the QAM symbols. The best performance is obtained by positioning the mean level of the demapped bits at a point that offers the best balance between clipping and quantisation. The decoder automatically handles shortening, puncturing and combining of repetitions.
The decoder operates on Z bits in parallel to process one code macro cell per clock cycle. The LDPC code is selected from pre-defined LUTs at the start of a packet and consists of a number of macro cells (e.g. 88 for WiFi) organised in rows. A complete decode iteration therefore takes numMacroCell active clock cycles but in the first iteration there is also a 'priming' delay due to the fact that the backward section lags the forward section by one row.
The forward and backward sections run in synchronisation but with a one row offset. The forward section 'accumulates' a check metric for the row and the backward section then uses this to create check responses and variable metrics. Each variable is 'used' several times in the code table so a complete iteration results in several updates of the variable metric, and a check response for each cell. The size of the variable metrics memory is the code size (n words) and the check response memory is numMacroCell words of Z*llrWidth bits.
The check response is the key element of the decode algorithm. When a bit is used in a parity check equation it is possible to calculate its probable value based on the estimates of the other bits used in that equation. The check metric is just an intermediate number needed in the calculation of the check response.
Check metrics and responses are calculated using variable estimates called variable responses. For any given cell the variable response is the relevant variable metric with the check response subtracted out to ensure indepedence. Clearly variable estimates can be calculated on the-fly and we do this in the forward section to create the check metric, however the data is also needed in the backward section to generate the check response (chkMetric - varResp) and so the required information is passed with a FIFO.
The block diagram illustrates the processing blocks and memories. Most layered LDPC decoder's are likely to appear similar at this high level, however most of the design effort is the refinement of the min-sum corrections, scaling method and scheduling strategies to produce an economic design that also performs well.