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5ps Jitter Programmable PLL in CSM 65nm G
Low Noise, Low Jitter Programmable PLL
Silicon Proven in CSM 65nm G
Jitter Below 5ps rms
Silicon Proven in CSM 65nm G
Jitter Below 5ps rms
Features
- 65nm CSM (Common Platform), Logic G Process
- Low Jitter <5ps rms
- Input Frequencies: 37.5MHz to 50MHz
- VCO Frequency Range: 900MHz to 1000MHz
- Output Clock Range: 60MHz to 1000MHz
- Power Down and Bypass Modes
- No External Components Required
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