The 5V General Purpose I/O libraries provide bidirectional I/O, analog I/O, and a full complement of I/O power, core power, and analog power cells along with the necessary support cells to construct a complete pad ring. The ability to isolate multiple power domains in the same pad ring is supported. These programmable I/O’s give the system designer the flexibility to design to a wide range of performance targets.
- • High performance, programmable general purpose I/O cells.
- • Inline and staggered CUP wire bond implementations with flip chip option
- • Power supply sequencing independent design with Power-On Control
- • Robust ESD Protection
- o 2KV ESD Human Body Model (HBM)
- ▪ Compliant with JEDEC specification JS-001-2012 (April 2012)
- o 200 V ESD Machine Model (MM)
- ▪ Compliant with JEDEC specification JESD22-A115C (November 2010)
- o 500 V ESD Charge Device Model (CDM)
- ▪ Compliant with JESD22-C101E (December 2009)
- • Latch-up Immunity
- o Compliant with JESD78D (November 2011)
- o Tested using I-Test criteria of ±100mA at maximum ambient temperature of +125°C.
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)