6-bit, 1 GSPS High Performance DAC in 28nm CMOS
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Block Diagram of the 6-bit, 1 GSPS High Performance DAC in 28nm CMOS
![6-bit, 1 GSPS High Performance DAC in 28nm CMOS Block Diagam](http://www.design-reuse.com/sip/blockdiagram/47545/9-main-6-bit-1-GSPS-High-Performance-DAC-in-28nm-CMOS.png)
Analog & Mixed Signal IP
- USB2.0 Host Transceiver PHY
- Analog Front End: 16x 12-bit 200 MSPS ADCs, 14x Voltage DACs, 4x 250 MSPS DACs, 4x TVM, LDO
- Analog Front End: 2x 12-bit 4 GSPS IQ ADCs, 2x 12-bit 8GSPS IQ DACs, bandgap, temp sensor, PLL, 4 x LDO
- Fibre-Channel Transceiver
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Analog Front End: 8x 12-bit 2 GSPSADCs, 4x 12-bit 200 MSPS ADCs, TVM, PLL, LDO