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6 track Ultra High Density standard cell library at TSMC 55 nm
Foundry Sponsored, TSMC 55 LeFP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
Features
- Ultra High-Density
- 7% up to 15% denser after P&R than standard 7-Track library
- Hand tuned cells, designed with 6-Track for optimal area reduction
- Pulsed latches as ?Spinner Cells? instead of flip-flops: for min. 30% gain in density
- Metal 1 power rails
- With smooth implementation
- Pulse generation automated by the script for ?Insert pulse generation?
- Spinner cell design minimizing hold time violations
- Ideal for slow to medium speed logic blocks
- Flexibility and ease of integration
- Multi VTs (SVT, LVT and HVT MOS versions) to deliver optimal performance, power and area results
- Support of CCS timing and power
- Complete set of PVT corners including temperature inversion corners, multi VDD characterization, custom PVT support
View 6 track Ultra High Density standard cell library at TSMC 55 nm full description to...
- see the entire 6 track Ultra High Density standard cell library at TSMC 55 nm datasheet
- get in contact with 6 track Ultra High Density standard cell library at TSMC 55 nm Supplier
standard cell
- DesignWare HPC Design Kit contains high-speed and high-density memory instances and standard cell libraries
- 40nm Low Leakage VHS, Channel Length 40nm, HVT Logic Process Standard cell Library
- 40nm Low Leakage VHS, Channel Length 40nm, HVT Logic Process Standard cell Library
- 40nm Low Leakage VHS, Channel Length 40nm, LVT Logic Process Standard cell Library
- 40nm Low Leakage VHS, Channel Length 40nm, PEK, LVT Logic Process Standard cell Library
- 40nm Low Leakage VHS, Channel Length 40nm, PEK, ULVT Logic Process Standard cell Library
