TSMC 65 LP, SESAME uHD for ultra high-density logic design thanks to 6-track cells combined with pulsed latch cells acting as spinner cells (densest alternative to flip-flops).
- Ultra High Density
- Up to 15% smaller area after P&R compared to standard 7-Track library
- Pulsed latches as ?Spinner Cells? instead of D-flipflops: for 30% gain in density
- Metal layer 2 available for routing as only Metal 1 used for cell design
- 6-Track cells for optimal area reduction
- Power reduction features:
- 6 times less leaky than standard 7-Track library at 1.2 V+/-10%
- Less consumption of dynamic power with 6 rather than usual 7 Tracks at 1.2 V+/-10%
- Easy implementation:
- Pulse generation automated by the script for ?Insert pulse generation?
- Spinner cell design minimizing hold time violations
- Optimal Design for Yield:
- Design methodology ensuring High-Yield circuits despite Mismatch