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Controller Area Network with Flexible Data-Rate (CAN / CAN FD) IP Core
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64/256 state block Viterbi decoder
The VA08S is a low complexity 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed to efficiently decode short block lengths with maximum flexibility, allowing it to decode various communications standards, as well as custom coding solutions.
Features
- 64 or 256 state (constraint length 7 or 9) Viterbi decoder
- Up to 213 MHz internal clock
- Rate 1/2, 1/3, or 1/4 (inputs can be punctured for higher rates)
- 4–bit received signed magnitude data
- Up to length 64 block decoding including tail
- Estimated channel bit error outputs
- 725 slices and 4 BlockRAMs (Virtex, Virtex-E, Spartan-II, Spartan-IIE), 670 slices and 1 BlockRAM (Virtex-II, Virtex-II Pro) or 707 slices and 1 BlockRAM (Spartan-3, Virtex-4)
- Asynchronous logic free design
- Available as EDIF core and VHDL simulation core for Xilinx Virtex, Virtex-E, Spartan-II, Spartan-IIE, Virtex-II, Virtex-II Pro, Spartan-3 and Virtex-4 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
- Low cost university license also available
- 64 State Features
- Up to 17.6 Mbit/s decoding speed
- Optional or standard code polynomials
- 256 State Features
- Up to 5.3 Mbit/s decoding speed
- Optional or 3GPP/3GPP2 code polynomials
Deliverables
- EDIF Core
- VHDL Simulation Core
- Test Vector Generation Software
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