World’s First 64 Bit Floating Point FFT/IFFT Hardware Accelerator for N = 4096
- 64 Bit Precision, Floating Point Arithmetic based on IEEE 754
- Radix-2 implementation for samples up to N = 4096
- Dynamically Re-configurable for multiple sample sizes from N = 2 to 4096.
- Clock Frequency of 2.3 GHz with 28 nm technology
- Throughput of one sample output for every clock cycle.
- Initial Latency, Area and RAM size customized for specific customer requirements.
- LTE-Advanced, OFDM and for all such standards to evolve over the next decade.
Block Diagram of the 64 Bit Floating Point FFT/IFFT Hardware Accelerator for N = 4096