64-bit Multiprocessor with Level-2 Cache-Coherence
The AX25MP symmetric multiprocessor supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. Andes Coherence Unit (ACU) manages level-1 cache coherence, including I/O coherence for cacheless bus masters, and duplicated L1 tag to screen allocated lines for snoop queries. Other AX25MP features include ECC for level-1/2 memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™, StackSafe™ for software quality improvement, and QuickNap™, PowerBrake, and WFI for power management.
View 64-bit Multiprocessor with Level-2 Cache-Coherence full description to...
- see the entire 64-bit Multiprocessor with Level-2 Cache-Coherence datasheet
- get in contact with 64-bit Multiprocessor with Level-2 Cache-Coherence Supplier
Block Diagram of the 64-bit Multiprocessor with Level-2 Cache-Coherence IP Core
![64-bit Multiprocessor with Level-2 Cache-Coherence Block Diagam](http://www.design-reuse.com/sip/blockdiagram/47118/20190702082534-main-AX25MP.jpg)