64-bit RISC-V application processor core with 7-stage pipeline
The core includes integrated L1 data and instruction caches, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like all Codasip RISC-V cores it is possible to create custom instructions using Codasip Studio to extend the ISA and to generate corresponding hardware and software development kits.
Tensor Flow Lite Micro is supported
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Block Diagram of the 64-bit RISC-V application processor core with 7-stage pipeline

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